1. Field of the Invention
This invention relates generally to computer hardware and software and, more particularly, to a method for testing signal integrity on a printed circuit board (PCB) design.
2. Description of the Related Art
There is a constant drive within the computer industry to reduce signal integrity problems on printed circuit boards (PCBs). In particular, there is often a need to reduce signal integrity problems associated with parallelism or crosstalk in the design of PCBs. Parallelism or crosstalk involves the long parallel runs of traces interconnecting elements on the PCBs. The long parallel runs of traces may couple electrical noise onto one another. Often, after a PCB has been routed, the board designer has no easy way to verify that board has been routed according to the specified parallelism guidelines.
Conventionally, the board designer may eyeball the nets of traces one layer at a time. However, even if there is a way manually to identify the problem nets of traces, there is a very limited capability to quantify the severity of the problem. Without a method to quantify the severity of the parallelism problem, given that thousands of traces may be present in a device, the board designer may not know where to begin to fix the problem nets of traces.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided, the method comprising associating each net of traces in a list of nets of the traces on a routed PCB with a parallelism index value and sorting the list of the nets of the traces on the routed PCB based on the parallelism index values. The method also comprises providing a list of victim nets of traces on the routed PCB based on the parallelism index values, each of the victim nets on the list of the victim nets associated with at least one offending net of traces on the routed PCB.
In another aspect of the present invention, a system is provided, the system comprising a representation of a routed PCB having a plurality of nets of traces thereon and a list of nets of the traces on the representation of the routed PCB with a parallelism index value associated with each net of the traces in the list of the nets of the traces on the representation of the routed PCB, the list of the nets of the traces on the representation of the routed PCB sorted based on the parallelism index values. The system also comprises a list of victim nets of traces on the representation of the routed PCB provided based on the parallelism index values, each of the victim nets on the list of the victim nets associated with at least one offending net of traces on the representation of the routed PCB.
In yet another aspect of the present invention, a device is provided, the device comprising means for associating each net of traces in a list of nets of the traces on a routed PCB with a parallelism index value and means for sorting the list of the nets of the traces on the routed PCB based on the parallelism index values. The device also comprises means for providing a list of victim nets of traces on the routed PCB based on the parallelism index values, each of the victim nets on the list of the victim nets associated with at least one offending net of traces on the routed PCB.